1. Field of the Invention
The present invention relates to methods of manufacturing semiconductor devices and, more specifically, to a method of manufacturing a semiconductor device in which a memory device formed by a self alignment contact process and a logic device formed by a salicide process (such a semiconductor device is hereinafter referred to as "a mixed device") are arranged on the same semiconductor substrate.
2. Description of the Background Art
Recently, semiconductor devices are required to be smaller and highly integrated. Among memory devices such as DRAMs (Dynamic Random Access Memories), for example, there is a device which can even store information of 1 Gigabit in one chip.
Multimedia development requires that the semiconductor devices are smaller and light weighted while having complicated functions. To satisfy all of the above mentioned requirements, the latest semiconductor devices must be provided with various devices in one chip. The most typical example is that memory and logic devices are formed on the same semiconductor substrate in one chip.
Conventionally, various microminiaturization pattern forming techniques have been developed for memory devices such as DRAMs. Among these techniques, there is a self alignment contact (hereinafter abbreviated as "SAC") technique. Generally, an alignment error of masks is taken into account a process of forming a contact hole. For example, an opening pattern of a mask for a gate electrode and that for a contact hole in a source/drain region are designed to allow for a margin in alignment. However, as SAC does not require consideration of alignment tolerance for the opening pattern of the mask, it is considered a significant technique for forming a memory device.
Now, referring to FIGS. 58A to 66A as well as FIGS. 58B to 66B, a conventional SAC process for a DRAM device will be described.
FIGS. 58A to 66A show memory cell regions, whereas FIGS. 58B to 66B show peripheral circuit regions or the like which are outside the memory cell regions. In the conventional SAC process of the DRAM device, first, as shown in FIGS. 58A and 58B, an isolation oxide film 102 is formed by trench isolation in well regions 101a and 101b in a semiconductor substrate. A gate insulating film 103 is formed by thermal oxidation or the like in a device formation region which has been separatedly formed by isolation oxide film 102. Then, a gate electrode 104 and an insulating film 105 including a silicon nitride film are formed by using the same mask. A source/drain region 106a is formed in a p well region 101a by implanting n type impurities by means of ion implantation or the like. In addition, a source/drain region 106b is formed in an n well region 101b by implantation of p type impurities.
Thereafter, as shown in FIGS. 59A and 59B, a silicon oxide film 107 and silicon nitride film 108 are sequentially formed to cover a main surface of the semiconductor substrate. In forming silicon oxide film 107, any of CVD (Chemical Vapor Deposition) and oxidation may be used.
As shown in FIGS. 60A and 60B, a resist film is formed on silicon nitride film 108. Thereafter, the resist film is subjected to photolithography for forming an n type transistor region other than in the memory cell region. Then, the resist film in the n type transistor region other than in the memory cell region is etched. A resist film 109 is formed in the n type transistor region in the memory cell region and in the p type transistor region other than in the memory cell region. Then, silicon nitride film 107, silicon oxide film 108 and gate insulating film 103 are subjected to anisotropic etching using resist film 109 as a mask. A sidewall nitride film 108a of a transistor is thereby formed. Then, n type impurities are further implanted to the n type transistor region in the memory cell region using insulating film 105 and sidewall nitride film 108a as masks, so that source/drain region 106a comes to have an LDD (Lightly Doped Drain) structure.
Then, a resist film is formed to cover an entire surface of the semiconductor substrate. The resist film is subjected to photolithography for forming a p type transistor region other than in the memory cell region. The resist film in the p type transistor region other than in the memory cell region is etched. Thus, a resist film 110 is formed. Silicon nitride film 108 is subjected to anisotropic etching using resist film 110 as a mask, so that a sidewall nitride film 108b is formed. Then, the p type impurities are further implanted to the n type transistor region using insulating film 105 and sidewall nitride film 108b as masks in the p type transistor region, so that source/drain region 106b comes to have the LDD structure. As a result, the structure as shown in FIGS. 61A and 61B is obtained. Here, the conductivity type of the well region and that of impurities to be implanted are not limited to the above mentioned conductivity type, and mutually opposite conductivity types may be employed. Then, resist film 110 is removed.
As shown in FIGS. 62A and 62B, a silicon oxide film including boron and phosphorus, that is, a BPSG (Boro Phospho Silicate Grass) film 111 is formed to cover the entire surface of the semiconductor substrate. Thereafter, the surface of BPSG film 111 is subjected to a thermal treatment or a planarization process such as CMP (Chemical Mechanical Polishing). A silicon oxide film 112 is formed on BPSG film 111.
Successively, a resist film is formed on silicon oxide film 112. As shown in FIGS. 63A and 63B, a resist film 113 is formed in a pattern for forming a self alignment contact opening between gate electrodes in the memory cell region.
Referring to FIGS. 64A and 64B, silicon oxide film 112 and BPSG film 111 are subjected to anisotropic etching using resist film 113 as a mask and silicon nitride film 108 as an etching stopper in the memory cell region. As shown in FIGS. 65A and 65B, resist film 113 is removed.
Now, referring to FIGS. 66A and 66B, silicon nitride film 108 and silicon oxide film 107 are sequentially subjected to anisotropic etching using silicon oxide film 112 and BPSG film 111 as masks. Thus, a self alignment contact hole 114 is formed. A conductive material (not shown) for forming an interconnection layer for a bit line or the like is buried in self alignment contact hole 114. As a result, source/drain region 106a formed in the semiconductor substrate and other conductive layers are electrically connected.
On the other hand, in the logic device formation region, to simultaneously reduce a parasitic resistance of the source/drain region and an interconnection resistance of the gate electrode, a technique referred to as salicide (Salicide: Self-aligned Silicide) for forming selectively and in a self-aligning manner a refractory metal silicide film on the surface of the gate electrode in the source/drain region. Referring to FIGS. 67 to 72, the salicide process will be described.
A method of manufacturing the structure shown in FIG. 67 is performed in a similar manner as that of forming the region other than the memory cell region shown in FIGS. 58B to 61B.
As shown in FIG. 68, a silicon oxide film 115 including a salicide protection film is formed to cover the entire surface of the semiconductor substrate. Then, a resist film is formed to cover the entire surface of the semiconductor substrate. Photolithography is performed such that the resist film is left only in the portion where silicon oxide film 115 is to be left. By etching the resist film not in the portion where silicon oxide film 115 is to be left, a resist film 116 is formed as shown in FIG. 69. Silicon oxide film 115 is subjected to anisotropic etching using resist film 116 as a mask. Resist film 116 is removed. This results in the structure shown in FIG. 70. Successively, referring to FIG. 71, a refractory metal silicide film 117 such as a cobalt silicide film or a titanium silicide film is formed on an active region of the exposed semiconductor substrate. Then, a BPSG film 118 is formed to cover the entire surface of the semiconductor substrate. BPSG film 118 is subjected to a thermal treatment or a planarization process such as CMP. A silicon oxide film 119 is formed on BPSG film 118. This results in a structure shown in FIG. 72.
Conventionally, in manufacturing a semiconductor device in which a memory device formed by SAC and a logic device formed by a salicide process are arranged in the same semiconductor substrate, the following problems arise. Referring to FIGS. 73A to 81A as well as FIGS. 73B to 81B, the problems associated with such mixed devices will be described. FIGS. 73A to 81A show memory device formation regions, whereas FIGS. 73B to 81B show logic device formation regions.
A method of manufacturing the structure shown in FIGS. 73A and 73B is performed in a manner similar to that of manufacturing the memory device which has been described with reference to FIGS. 58A to 61A as well as 58B to 61B. As shown in FIGS. 74A and 74B, a silicon oxide film 120 corresponding to a salicide protection film of the logic device is formed to cover the entire surface of the semiconductor substrate. Then, a resist film 121 is formed to cover the entire surface of the semiconductor substrate. The resist film in the portion where silicon oxide film 120 is to be left in the logic device formation region is subjected to photolithography. By etching the resist film, a resist film 121 is formed. This results in a structure shown in FIGS. 75A and 75B.
Silicon oxide film 120 is subjected to anisotropic etching using resist film 121 as a mask. Resist film 121 is removed. This results in a structure shown in FIGS. 76A and 76B. Silicon oxide film 120 is left on an inner wall of a recess formed by silicon nitride film 108 as a side wall oxide film in the memory device formation region. In addition, a thickness of silicon nitride film 108 on silicon nitride film 105 is reduced as silicon oxide film 120 has been over etched.
As shown in FIGS. 77A and 77B, a refractory metal silicide film 122 is formed in an active region where the semiconductor substrate is exposed in the logic device formation region. Then, a BPSG film 123 is formed to cover the entire surface of the semiconductor substrate. BPSG film 123 is subjected to a thermal treatment or a planarization process such as CMP. A silicon oxide film 124 is formed on BPSG film 123. This results in a structure shown in FIGS. 78A and 78B. A distance between inner walls of the recess formed by silicon nitride film 108 is small as silicon oxide film 120 is left on the inner wall of the recess formed by silicon nitride film 108. Thus, an aspect ratio of the recess formed by silicon nitride film 108 is high. As a result, BPSG film 123 is not completely filled in the recess formed by silicon nitride film 108. Thus, a cavity 125 is formed in BPSG film 123 in the recess formed by silicon nitride film 108.
Referring to FIGS. 79A and 79B, a resist film is formed to cover the entire surface of the semiconductor substrate. The resist film is subjected to photolithography for patterning the self alignment contact opening in the memory device formation region. By etching to remove the resist film in the self alignment contact opening, a resist film 126 is formed in a pattern. Thereafter, as shown in FIGS. 80A and 80B, silicon oxide film 124 and BPSG film 123 are sequentially subjected to anisotropic etching. A resist film 126 is removed. Silicon nitride film 108 and silicon oxide film 107 are subjected to anisotropic etching using silicon oxide film 124 and BPSG film 123 as masks. Thus, a self alignment contact opening 127 is formed. This results in the structure shown in FIGS. 81A and 81B.
As described above, in the conventional mixed device, silicon oxide film 120 which has been formed as the salicide protection film is left on the inner wall of the recess formed by silicon nitride film 108 in self alignment contact opening 127. Generally, it is difficult to etch the silicon oxide film as it does not include impurities such as boron or phosphorus. In addition, essentially, the portion near the inner wall of the recess formed by silicon nitride film 108 is difficult to be etched. Thus, silicon oxide film 120 would not be etched but left. As a result, an aspect ratio of self alignment contact opening 127 is high. A conductive material (not shown) cannot accurately be buried in self alignment contact opening 127. Consequently, good electric connection of an interconnection layer (not shown) formed in self alignment contact opening 127 and source/drain 106a is not achieved.
Further, in the memory device formation region, a distance between the inner walls of the recess formed by silicon nitride film 108 is reduced by the left silicon oxide film 120. The aspect ratio of the recess formed by silicon nitride film 108 increases. As a result, cavity 125 is formed in BPSG film 123 in the recess formed by silicon nitride film 108 as described above. Cavity 125 prevents transistors to be surely insulated, thereby disadvantageously reducing reliability of the semiconductor device.
In addition, in the mixed device, over etching silicon oxide film 120 in the memory device formation region may result in a reduced thickness of silicon nitride film 108 or removal of silicon nitride film 108, depending on the situation. Therefore, an upper surface of gate electrode 104 may be exposed. If gate electrode 104 is exposed, a short circuit between the interconnection layer formed in self alignment contact opening 127 and gate electrode 104 is caused.
Therefore, in manufacturing a mixed device, it is important to make use of the process which has been used for each device to the full while not making the process unnecessarily complicated.